1. Field of the Invention
This invention relates to processors, and, more particularly, to microcode implementation within processors including multiple processor cores.
2. Description of the Related Art
As processor implementation evolves, it is becoming increasingly common to attempt to increase processor performance by replicating individual processor cores within a processor. Such cores may be capable of independent instruction execution, increasing the coarse-grained parallelism available for application execution with less cost and design complexity than may be required by alternative strategies for increasing performance, such as increasing fine-grained parallelism or execution frequency.
Multiple-core processor implementations present certain design challenges of their own, however. Certain processor core resources, such as storage resources for microcode routines, may be included in critical timing paths such that proximity of the resource to a given core may directly affect the operating frequency of the given core. Sharing a single instance of such storage resources among multiple cores may thus degrade the performance of the cores by increasing the latency to the shared instance. However, replicating a storage resource such that each core includes its own instance of the resource may be costly in terms of design area, power and/or other design figures of merit.